//----------------------------------------------------------------------
//import code_parameter::*;
//----------------------------------------------------------------------
`include "list_of_parameters.h"
module CAB 
(
	input  wire                            	a,
	input  wire                            	b,
//----------------------------------------------------------------------
	output wire                            	c,
//----------------------------------------------------------------------
	input  wire [WIDTH - 1:0]              	A,
	input  wire [WIDTH - 1:0]              	B,
	input  wire [WIDTH - 1:0]              	C,
//----------------------------------------------------------------------
	output reg  [WIDTH*2 :0]              	DATA_OUT,



//----------------------------------------------------------------------
	input  wire							   	d,
	input  wire                            	clk,
	input  wire                            	reset,
//----------------------------------------------------------------------
	output reg                             	out);
	
	reg  [WIDTH*2 - 1:0]                    DATA_OLD;
	reg	 [WIDTH - 1:0]				        REG_C;
	reg	 [WIDTH -1: 0]						REG_D; 											

//	Mult (
//		.clock                                                  (clk),
//		.dataa													(A),
//		.datab													(B),
//		.result													(DATA_OLD));

//task 2
	assign c = a * b;

//task 3
	always @ (negedge reset or posedge clk)
	begin: TASK3
		if(!reset)
			out <= 0;
		else
			out <= d;
	end

//task 4	
	always @(negedge reset or posedge clk) 
	begin: TASK4
		if(!reset)
		begin 		
			DATA_OUT             <= 0;
			REG_C                <= 0;
			REG_D                <= 0;
			DATA_OLD             <= 0;
		end
		else
		begin
		    REG_C                <= C;
			DATA_OLD             <= A*B;
			REG_D				 <= REG_C;
			DATA_OUT             <= DATA_OLD + REG_D;	
		end				
	end
		
endmodule
